1. Field of the Invention
Certain embodiments of the present invention relate to a video signal processing circuit for processing an input video signal to display reduced or enlarged video images within a display window, where the video signal processing circuit uses a buffer memory such as a field memory or a frame memory as a functional component of the video processing circuit. Other embodiments of the present invention relate to a video signal processing circuit capable of changing the magnification of a video image by applying a reduction ratio or a magnification ratio.
2. Description of the Related Art
Television displays presently provide a variety of display functions, including the well known "picture in picture (PIP) function" that allows the selective display of either a single video image covering the whole display window or a plurality of video images simultaneously displayed within the window of the display. With the introduction of multimedia applications for television displays, there is an increasing demand that television displays provide additional display functions. A particularly demanded function for television displays used in multimedia applications is the "window display function at an arbitrary reduction ratio," widely implemented as part of the operating environments of personal computers. Using an arbitrary reduction ratio to generate a child frame is difficult for most simple implementations of video processing circuits.
The display of multiple frames or images within a television display window requires that a video signal processing circuit include a buffer memory such as a field memory or a frame memory so that the display of the parent frame can be synchronized with display of the one or more child frames within the window. FIG. 9 shows a block diagram of a conventional video signal processing circuit that may be used for generating a reduced image for display in a child frame. The FIG. 9 circuit performs time based compression of a video signal to reduce the size of an image. Input processor 1 receives an input video signal corresponding to an image to be displayed in a child frame within the window of the display. The input processor 1 processes the input video signal according to a value of the reduction ratio K to generate a reduced video signal that is sized to fit within the child frame. Within the input processor, the reduction processing is performed with an internal filter circuit 10. The reduced video signal output from the filter is written into the field memories 2 and 3. Control block 4 provides an input video clock generator 5 that controls the writing of signals to the field memories 2 and 3, and a display video clock generator 6 that controls the reading of signals from the field memories 2 and 3. By using independent clocks for writing and reading signals from the field memories, it is possible to write and read the signals at different clock speeds, facilitating signal reduction (compression) or magnification (expansion). The reduction ratio data K are provided from a source external to the input video clock generator 5, which then provides the reduction ratio K to the input processor 1.
Input video clock generator 5 receives a horizontal synchronizing signal (or an input H) and a vertical synchronizing signal (or an input V). Input video clock generator 5 generates and outputs a write clock WCLK having the same rate as a pixel clock synchronized with the input H. The input video clock generator 5 also outputs write enable signals WE1 and WE2 for alternately enabling the field memories 2 and 3, switching between the field memories at a field display rate appropriate to effectively display the input video signal. Additionally, the input video clock generator outputs a write reset signal WRST for resetting the write addresses of the field memories 2 and 3 at the rise of the write enable signals. Field memories 2 and 3 are individually equipped with address counters for independently designating the write and read addresses for write and read operations so that video signal streams can be written to memories without external address generation. The write address counter within each of the field memories is reset by the signal WRST and generates write addresses by incrementing the write address counter in response to each of the write clocks WCLK issued while the enable signals WE1 and WE2 are at an H level. Consequently, the reduced video signal provided by the input processor 1 is written into the field memories 2 and 3.
Processing of the video signal to reduce an image may include selectively omitting pixels from the stream of pixels within the original video signal to produce the reduced video signal corresponding to the smaller child frame image. Pixels are omitted by controlling the write enable signals to prevent selected pixels from being stored in the memory. When the value of the reduction ratio K is "1," i e., when no reduction of the video image is to be performed, the write enable signals WE1 and WE2 are kept at the H level for the effective video period. When the value of the reduction ratio K is lower than "1," the H-level periods of the enable signals WE1 and WE2 are controlled according to the value of the reduction ratio K. If the value of the reduction ratio K is "1/2," for example, the enable signals WE1 and WE2 are cycled between the H level and the L level at every other pixel, as shown at (b) and (c) in FIG. 10. Input video clock generator 5 also calculates image size data SIZ appropriate to the child frame on the basis of the value of the reduction ratio K and transmits the data SIZ to the display video clock generator 6. If the number of horizontal pixels and the number of vertical pixels of the input video signal are "640" and "480," respectively, and if the value of the reduction ratio K is "1/2", for example, the image size data SIZ are "320" and "240," respectively, for the horizontal SIZ(H) and the vertical SIZ(V). Thus, 240 lines of video signal with each line including 320 pixels will be stored in the field memories when the child image is displayed in a frame having X and Y dimensions reduced in length to one half of the dimensions of the display window.
To read the reduced video signals from the field memories, on the other hand, the display video clock generator 6 receives both the horizontal synchronizing signal (or the display H) and the vertical synchronizing signal (or the display V) of the display video signals or of the parent frame. The display video clock generator 6 also receives the display position data (X, Y) indicating the display position of the reduced child frame within the window. Display video clock generator 6 outputs a read clock RCLK having the same rate as a pixel clock synchronized with the display H. Display video clock generator 6 outputs read enable signals RE1 and RE2 that alternately enable the field memories 2 and 3, switching between the field memories at a field display rate appropriate for the effective display of the display video signals. Display video clock generator 6 also outputs a read reset signal RRST for resetting the read addresses of the field memories 2 and 3 at the rise of the read enable signals. Following the reset at the beginning of data reading, the reading address counters in the field memories 2 and 3 generate successive read addresses by incrementing the read address for each cycle of the read clock RCLK that occurs while the enable signals RE1 and RE2 are at the H level. Successive addresses are thus addressed and the reduced video signals are read out from the field memories 2 and 3. Here, the display H and the display V may be generated, if known in advance, by the display video clock generator 6 so that the various signals RRST, RCLK, RE1 and RE2 may be generated on the basis of the display H and display V signal.
FIG. 11 illustrates a conventional picture-in-picture television display with a child frame image A displayed on the window. As shown, the display position data (X, Y) indicates the display position of the child frame on the parent frame for the displayed video signal, and image size data SIZ (H, V) indicate the size of the child image and frame of the input video signals to be next displayed in the window. On the basis of the image size data SIZ (H, V) and the image position data (X, Y), the display video clock generator 6 sets the aforementioned read enable signals RE1 and RE2, as shown at (e) and (f) in FIG. 10, to the H level only for the effective display period so that the display of FIG. 11 may be realized. In this case, the H level is continuously outputted, in contrast to the selective write enable used when writing data into the field memories 2, 3. Moreover, the image size data SIZ and the image position data (X, Y) are transmitted from the display video clock generator 6 to a display processor 7 located downstream of the field memories 2 and 3. Display processor 7 performs display processing for the window display, such as framing the reduced video signals read out from the field memories or adding background data to be displayed with the video image, and the result from the display processor is outputted as display video signals.
In order to change the reduction ratio arbitrarily, as would be required for the display of child images in an arbitrarily sized child frame, the processing content has to be changed at both the input side and the display side of signal processing circuit in accordance with the newly input reduction ratio data. In other words, new video signals processed according to the new reduction ratio data must be input to the field memories 2, 3 from the input side, and new SIZ and image position data (X, Y) must be provided to the display processor 7 on the display side before a new image according to the new reduction ratio data can be displayed. However, the presently displayed image is disturbed if the processing content is changed during the actual writing and reading actions. In order to prevent this disturbance, the change in the reduction ratio is performed during the vertical blanking interval. Since the input V and the display V are not synchronized, however, the change in the reduction ratio has a time distortion between the write side and the read side. If a new reduction ratio K is input at time T1 when the phase of the display V is delayed from the input V, as shown at (a) and (d) in FIG. 10, the reduction ratio is changed at the input video clock generator 5 and the input processor 1 during a vertical blanking interval NP1 just after T1, and subsequent reduction and write control operations are performed according to the changed reduction ratio. In the display video clock generator 6 and the display processor 7, however, the reduction ratio is changed for a vertical blanking interval DP1 just after T1. The timing of the change of the processing content on the display side comes after the changing time NP1 at the input side so that the video signals, as written according to the changed reduction ratio, are subjected to the display processing on and after DP1.
If, on the other hand, the new reduction ratio data are input at time T2 after the vertical blanking interval NP1 for the input V and before the vertical blanking interval DP1 for the display V, as shown in FIG. 12, the reduction ratio is changed in the input video clock generator 5 and the input processor 1 for the vertical blanking interval NP2 after T2. In the display video clock generator 6 and the display processor 7, the change in the reduction ratio is performed during the vertical blanking interval DP1 before NP2, prior to the change in the reduction ratio at the input side. For the display period after the change (DP1) in the reduction ratio, therefore, the video signals before the change in the reduction ratio are to be displayed, thereby seriously distorting the image displayed in the child frame. This raises a problem that the reduction ratio cannot be changed if the child frame is to be continuously displayed.
In Japanese Patent Application No. 7-267107, therefore, we have proposed a reduced video signal processing circuit for controlling the reading of a reduced video signal, if the reduction ratio is changed, on the basis of image size data based on the changed reduction ratio. The described system accomplishes this function by writing the image size data within a header associated with the reduced video signals stored in a buffer memory so that the image size data can be read at the display side particularly corresponds to the reduced video signal. According to this construction, after the image size data are fixed, the display can be reliably processed at the display side using the new reduction ratio associated with the video signals for which the reduction ratio has been changed. However, the image size data stored in the header are determined by counting the horizontal write enable signal WEH and the vertical write enable signal WEV used in generating the write enable signals WE1 and WE2, respectively, for one horizontal period of the input H and for a one-field period of the input V. For the one-field period just after the change in the reduction ratio, therefore, the video signal is necessarily that which is processed at the new reduction ratio, but the image size data cannot immediately be adjusted for the data after the change in the reduction ratio, so that the reduction ratios are different between the reduced video signal to be written in the buffer memory and the image size data in the header associated with that reduced video signal.
If an address passing phenomenon occurs between the write address and the read address for the buffer memory, on the other hand, the reduction ratios become unequal between the image size data added as the header and the accompanying reduced image signals. This may result in display of a distorted image.
The problems thus far described may occur not only in a reducing process but may also occur in an enlarging process.